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Ordering number : EN*5382
CMOS LSI
LC89210
High-speed fax modem data pump
Preliminaly Overview
The LC89210 is a highly integrated modem engine that can be used in products that support transmission rates up to the 14,400 bps rate used in contemporary group III fax equipment. The LC89210 is compatible with V.21, V.23 and Bell 103 full-duplex modems.
Package Dimensions
unit: mm 3213-PQFP64
[LC89210]
Features
* Supports the ITU-T V.17, V.29, and V.27ter fax standards * ITU-T V.23, V.21, and Bell 103 * V.17, V.29 (T104), and V.27ter short training * V.33 half duplex * 1800-Hz or 1700-Hz carrier * The LC89210 is a complete data pump on a single chip. * 5 V single-voltage power supply -- Operating power dissipation: 375 mW (typical) -- Low power mode: 5 mW (typical) * Expanded operating modes -- Full implementation of V.17, V.33, V.29, and V.27ter handshaking -- Autodial and autoanswer functions -- Programmable tone detection and FSK V.21 flag pattern detection during high-speed reception -- Programmable call progresss and call waiting tone detection, including DTMF -- Support for programmable CLASSTM detection -- Wide dynamic range (better than 48 dB) -- A-law voice PCM mode * Multiple interfaces -- Parallel 64 x8-bit dual-port RAM -- Synchronous/HDLC parallel data processing -- Support for HDLC framing -- V.24 interface -- Can monitor all operating states in real time. -- Includes all diagnostic functions. -- Dual 8-bit D/A converter for eye pattern display
SANYO: PQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
52696HA (OT) No. 5382-1/10
LC89210
Specifications
Electrical Specifications at Ta = 25C, VDD = 5 V (unless otherwise specified) Absolute Maximum Ratings with respect to ground
Parameter DC supply voltage Digital or analog input voltage Digital or analog input current Digital output current Analog output current Allowable power dissipation Operating temperature Storage temperature (plastic) Symbol VDD VI, VIN II, IIN IO IOUT Pd max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to (VDD + 0.3) 1 20 10 1000 0 to +70 -40 to +125 Unit V V mA mA mA mW C C
Electrical Characteristics at Ta = 0 to +70C, VDD = 5.0 V 5%, GND = 0 V (unless otherwise specified)
Parameter Symbol Conditions min typ max Unit [Power Supply and Common-Mode Voltages] Supply voltage Current drain Current drain in lower power mode Common-mode voltage VDD IDD IDD-ip VCM VIL VIH IL IH VIL VIH II VOH VOL IOZ CIN VREF VCMOin VDIFin VCMOout VDIFout VOFFout Rin Rout RL CL VREFP - VREFN V = (RXA1 + RXA2)/2 - VCM RXA1 - RXA2 (TXA1 + TXA2)/2 - VCM TXA1 - TXA2 (TXA1 - TXA2) RXAX TXAX TXAX TXAX 10 50 -100 100 20 -200 2.40 -300 VI = VDD or VI = GND Ilord = 2 mA Ilord = 2 mA GND < VO < VDD -50 0 5 GND < VI < VIL max VIH min < VI < VDD -0.3 2.2 -10 2.4 0.4 +50 0 +10 3.5 -15 15 VDD/2 - 5% 4.75 5 75 1 VDD/2 VDD/2 + 5% 1.5 5.25 100 V mA mA V
[Crystal Oscillator Interface] XTAL and EXTAL Input low-level voltage Input high-level voltage Input low-level current Input high-level current V V A A
[Digital Interface] All digital pins except the XTAL pin Input low-level voltage Input high-level voltage Input current Output high-level voltage Output low-level voltage 3-state input leakage current Input capacitance [Analog Interface] Differential reference voltage input Input common-mode offset Differential input voltage Output common-mode voltage offset Differential output voltage Differential output DC offset Input resistance Output resistance Load resistance Load capacitance 2.50 2.60 +300 2 x VREF +200 2 x VREF +100 V mV Vp-p mV Vp-p mV k k pF +0.8 V V A V V A pF
No. 5382-2/10
LC89210 Pin Assignment
Host Interface The LC89210 is interfaced to the control processor through a 64-byte dual-port RAM that is shared by the LC89210 and the host.
Pin SD0 to SD7 SA0 to SA6 SDS (SDR) SR/W (SWR) SCS SDTACK SINTR RESET RING INT/MOT Note: * Open-drain output Type I/O I I I I OD* OD* I I I System data bus System address bus System data strobe System read/write System chip select System bus data acknowledge System interrupt request Reset. This is an active-low signal. Ring detect signal Intel/Motorola interface Function
No. 5382-3/10
LC89210 Analog Interface
Pin TXA1 TXA2 RXA1 RXA2 VCM VREFN VREFP Type O O I I I/O I I Transmission analog output 1 Transmission analog output 2 Reception analog input 1 Reception analog input 2 Analog common voltage (nominal value: +2.5 V) Analog negative reference voltage (nominal value: CM - 1.25 V) Analog positive reference voltage (nominal value: CM + 1.25 V) Function
V.24 Interface
Pin RTS CLK CTS RXD TXD CD Type I O O O I O Transfer request. This is an active-low signal. Data bit clock Clear to send. This is an active-low signal. Reception data Transfer data Carrier detect. This is an active-low signal. Function
Other Interfaces
Pin XTAL EXTAL EYEX EYEY TEST1 TEST2 Type O I O O Internal oscillator output Internal oscillator input or external clock Constellation X analog coordinate (eye pattern) Constellation Y analog coordinate (eye pattern) This pin must be left open This pin must be left open Function
Note: The LC89210 nominal external clock frequency is 29.4912 MHz. This value has a precision of 5.10-5.
Boundary Scan Interface The LC89210 provides 13 signals for testing. These signals can be used along with the SGS-Thomson ST18932 boundary scan development tools in the product development process to debug application hardware and software. If this function is not used, all of these input signal must be connected to ground, and all of these output signals must be left open.
Pin SCIN SCCLK SCOUT BOS EOS MC0 to MC2 HALT MC1 RDYS EBS CLKOUT Type I I O I I I I O O I O Scan data input Scan clock Scan data output Scan control start Scan stop Mode control LC89210 execution step Multi-cycle instruction Scan flag ready Enable boundary scan LC89210 internal clock (the crystal oscillator frequency divided by 2) Function
No. 5382-4/10
LC89210 Power Supply
Symbol VDD GND AVDD AGNDT AGNDR Digital +5 V (pins 9, 25, and 41) Digital ground (pins 8, 24, and 40) Analog +5 V (pin 62) Analog transmission system ground (pin 64) Analog reception system ground (pin 59) Parameter
Block Diagrams
Function Block Diagram
Hardware Block Diagram
No. 5382-5/10
LC89210 AC Electrical Characteristics Dual-Port RAM Host Timing
Parameter Address and control setup time SDTACK acknowledge Data setup time Address and control hold time Data hold time SDTACK hold time Write enable low state Access inhibition high state Read enable low state Read data access SINTR clear delay Data valid to tristate
Number 1 2 3 4 5 6 7 8 9 10 11 12
Conditions
min 5
typ
max
Unit ns
20 10 0 5 0 45 70* 45 35 50 15
ns ns ns ns ns ns ns ns ns ns ns
Note: * The minimum delay of 70 ns is the time from the rising edge of NWRITE to the next falling edge on either NREAD or NWRITE.
No. 5382-6/10
LC89210 Serial V.24 Interface Timing
Parameter TXD to CLK setup time TXD to CLK hold time RXD valid to CLK delay time RXD valid to CLK hold time
Number 1 2 3 4
Conditions
min 30 10
typ
max
Unit ns ns
100 0
ns ns
No. 5382-7/10
LC89210 Electrical Circuit Diagrams Oscillator We recommend the use of the following circuit if an overtone crystal oscillator is used in series resonance mode.
No. 5382-8/10
LC89210 Printed Circuit Board Design Guidelines While the two most important factors influencing the performance of this fax modem are the performance of the LC89210 itself and the appropriateness of the design of the printed circuit board, it is not the purpose of this section to describe all aspects of modem printed circuit board design. Rather, this section presents the following few recommendations. 1. 4-layer boards The digital and analog system grounds should be separated and then connected at a single point (single-point ground). Furthermore, the location of the single-point ground should be as close to the LC89210 as is possible. AGNDR and AGNDT should be connected to the single-point ground location with an extremely low impedance. 2. 2-layer boards Supply the ground grid to all empty spaces and the inner side of component spaces. 3. The 2.2 nF capacitors connected to the RXA1 and RXA2 pins should be located as close to the pins as possible. 4. The two 100 nF capacitors connected to the VREFP and VREFN pins should be located as close to the pins as possible. 5. To prevent latchup due to differences in power on timing between the analog and digital power supplies, insert two diodes with reverse polarities in parallel between the VDD (digital) and AVDD (analog) power supplies. Application Example
Note: The capacitors marked with asterisks (*) must be connected as close as possible to the LC89210 pins. Signal names ending in "I" are active low signals. If it is necessary to supply current to VCM, add the resistors R3, R4, R5, and R6.
No. 5382-9/10
LC89210
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5382-10/10

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